1. Field of the Invention
The present invention relates to a semiconductor device. Particularly, it relates to a semiconductor device provided with a startup element.
2. Description of the Background Art
A switching power supply control IC which controls an individual high breakdown voltage switching transistor has been disclosed as a semiconductor device, for example, in JP-A-2008-153636. When the IC is operating, the IC operates the high breakdown voltage switching transistor to thereby form its own power supply. However, when the IC is started up, a startup current must be supplied thereto from a startup circuit. The startup circuit is usually integrated in the same semiconductor substrate as the switching power supply IC. With this configuration, it is possible to reduce the number of components and simplify the power supply system.
The startup current is a current formed by rectifying an input AC signal of AC 100 V to 240V. In order to supply the startup current to the startup circuit, an upstream normally-on type startup element of the startup circuit requires a breakdown voltage not lower than 450 V. The normally-on type startup element is made monolithic with the switching power supply control IC so as to be implemented as a lateral type high breakdown voltage junction field effect transistor (JFET). Design specifications of the switching power supply apparatus are determined based on the current driving capability of the JFET.
Further improvement of the reliability is also requested in the switching power supply control IC. Improvement of breakdown resistance to electrostatic discharge (ESD) of the JFET is important for improvement of the reliability of the switching power supply control IC. However, an external input terminal (bonding pad) electrically connected to a drain region of the JFET is provided on the JFET in this kind of switching power supply control IC. Therefore, it is difficult to form an ESD protection element in parallel with the JFET. For this reason, the JFET itself has to ensure the breakdown resistance to ESD. So far, there has been used a method in which the planar size of the JFET is increased and the distance between the external input terminal and a source region of the JFET, that is, the length of a drift region, in the planar pattern is elongated to improve the breakdown resistance to ESD. However, the chip size in this method becomes large. Therefore, an acquisition rate of chips which can be obtained from one piece of semiconductor wafer is decreased to thereby result in the increase of the cost.